1. Field of Invention
The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a charge-trapping memory.
2. Description of Related Art
Flash memory is a type of non-volatile memory that allows multiple data reading, writing and erasing operations. In addition, the stored data are retained even after power to the device is terminated. With these advantages, flash memory has been broadly applied in personal computers and electronic equipment.
A conventional flash memory is a device having a dual-gate structure, in which a first gate electrode that functions as a floating gate electrode is formed on an oxide film disposed on the surface of a semiconductor substrate, an interlayer insulating film is disposed on the upper surface of the first gate electrode, and a second gate electrode that functions as a control gate electrode is formed on the upper surface of the interlayer insulating film. In the dual-gate structure of this type of memory cell, charges are accumulated in the floating gate, which is made of, for example, polysilicon, and information is stored by altering a threshold voltage of the memory cell according to the accumulated charges therein. To program this type of memory cell, biases are applied to the control gate and the source/drain of the memory cell. An electron flow from the source to the drain produces hot electrons that tunnel through the tunnel oxide layer into the floating gate. The hot electrons are distributed evenly in the floating gate. If a defect occurs in the tunnel oxide film, the charges accumulated in the floating gate are likely to leak out, causing a destruction of the stored data.
To resolve the leakage problem of the flash memory, a charge-trapping layer is developed to replace the polysilicon floating gate in the conventional flash memory. The charge-trapping layer is, for example, a silicon nitride layer formed as a silicon oxide/silicon nitride/silicon oxide (ONO) structure. The memory cell with a stacked gate structure comprising a nitride charge-trapping medium is known as a “nitride read-only memory (NROM)”. Due to the highly-compacted nature of the nitride layer, hot electrons tunneling into the silicon nitride layer are trapped to form an unequal concentration distribution and are localized in a region of the silicon nitride layer near the drain with a Gaussian spatial distribution. Because the injected electrons are localized, they are less likely to locate at the defects of the tunnel oxide layer. Hence, a current leakage in the device can be mitigated. Moreover, since the electrons are localized in a region of the charge-trapping layer near the drain, a charge-trapping memory is capable of storing two bits in a single memory cell.
However, during the fabrication of a NROM, for example, in the processing steps of forming additional semiconductor structures or interconnects, the stacked gate structure is exposed to plasma processing, for example, in plasma etching, which causes electrical charges to accumulate on the interconnects due to a phenomenon known as the “antenna effect”. The accumulated charges on the interconnects create a voltage difference across the ONO layer of the NROM memory cell. When a transient charge imbalance occurs, charges are injected into the ONO layer such that a wide threshold voltage (Vt) distribution among memory devices is resulted.
In addition to the “antenna effect”, the clustering of electrons on the surface of an insulating film may lead to a wide threshold voltage distribution. For example, during the metal interconnect process of a NROM, an insulating layer is formed by a PECVD process to cover the metal lines. However, the plasma used in the PECVD process often causes a clustering of charges on the surface of the insulating layer, wherein these charges travels to the silicon nitride layer in the ONO layer along the metal lines. As a result, a wide threshold voltage distribution among memory devices is resulted.
Moreover, when an ultraviolet (UV) light is used for exposure during a photolithograph process, electron-hole pairs are generated, and some of the electrons diffuse into the charge-trapping layer. Ultimately, a wide threshold voltage distribution among memory devices is resulted.
FIG. 1 is a schematic diagram illustrating the threshold voltage distributions among memory devices that are not being charged versus being charged by plasma or UV light. As shown in FIG. 1, the threshold voltage distribution is narrow and the average threshold voltage is lower when the memory devices are not charged by plasma or UV. On the other hand, the threshold voltage distribution is broader and the average threshold voltage is higher when the memory devices are charged by plasma or UV. A wide distribution of the threshold voltage has serious consequences. For example, if a memory has a wide threshold voltage distribution, the program distribution and erase distribution may overlap with each other, leading to an abnormal function of the memory device.